• GE235Cpu

III. Functions of the basic GE-235 system components

Central Processor

Strage

Memory Organization

Memory Allocation

M-Register and Parity Checking

Arithmetic Unit

B-Register

1. The addend for addition
2. The subtrahend for subtraction
3. The multiplicand for multiplication
4. The divisor for division

A-Register

Q-Register

N-Register

C-Register (optional)

Control

I-Register

G-Register

P-Register

Functional Integration: THe Operating Cycle

1. Extracted from memory
2. Transferred to the proper register
3. Restored in memory

Operating Cycle Phases

Detailed Analysis of The Operating Cycle

1. AMP - logic used to address memory from the P-counter
2. AMX - logic used to address memory from one of the address modification waords
3. AMI - logic used to address memory from the I-register

Operator's Console

V. Machine Langage

Instruction Categories

• General Instruction (Require no access to memeory):
  • Data Transfer
  • Input/Output Operations
  • Most Internal Test-and-Branch Instructions
  • Shift Left or Right
• Instructions Requiring Access to Memory:
  • Arithmetic
  • Memory Transfers
  • Certain Test-and-Branch Instructions
  • Address Modifications

Data Transfer Format

• Operation Code : Always is 25(8) for General Instruction
  |    00:Usually No Address Modification*
  |    | 01:indicates Data Transfer Variation
  |    | | Specifies Exact Operation
  |    | | |
  0   000000         1
  S---456789---------9
  101010001

Input/Output Format

• Operation Code : Always is 25(8) for General Instruction
  |    Usually No Address Modification*
  |    | Designates Input/Output Variation
  |    | | Starting Address : Either a memory location or peripheral controller address
  |    | | |    Specific Operation : Designates the specific Input/Output operation
  |    | | |    |
  0   000000   11    1
  S---456789---34----9
  101010000

Test-and-Branch Format

• Operation Code : Always is 25(8) for General Instruction
  |    Usually No Address Modification*
  |    | Designates Test-andBranch Variation
  |    | | 1 = branch on negation (no) : 0 = branch on affirmation (yes)
  |    | | |Branch Condition : Specifies condition to be tested
  |    | | ||
  0   0000001        1
  S---4567890--------9
  101010011X

Shift Left or Right Format

• Operation Code : Always is 25(8) for General Instruction
  |    Address modification is possible
  |    | Shift Variation
  |    | | 1 = left shift :0 = right shift
  |    | | |Exact Operation : Specifies Registers 
  |    | | ||    Length of Shift : Up to 31 bit positions
  |    | | ||    |
  0   0000001   11   1
  S---4567890---45---9
  101010010X

Instruction

                Symbol  Opr     Operand                 
Pseudo-Instructions     *******         ALF     One BCD Word                    Alphanumeric
Pseudo-Instructions     *******         NAL     One BCD Word                    Negative Alphanumeric
Pseudo-Instructions     *******         MAL     One to 15 concecutive BCD Words                 Multiple Alphanumeric
Pseudo-Instructions     *******         PAL     One to 15 concecutive BCD Words with sign bit on in last word                   Multiple Alphanumeric for Printer with Print Line Indicator
Pseudo-Instructions     *******         DEC     One Fixed Point Binaly Number                   Decimal
Pseudo-Instructions     *******         DDC     One Double Length Fixed Point Binary Numbaer                    Double Length Decimal
Pseudo-Instructions     *******         FDC     One Floating Point Binary Number                        Floating Point Decimal
Pseudo-Instructions     *******         OCT     One Binary Word                 Octal
Pseudo-Instructions     *******         Z       One Binary Word                 Octal Operation Code
Control Line Pseudo-Instructions        *******         ORG     Decimal or Synbolic                     Origin
Control Line Pseudo-Instructions        *******         LOC     Octal                   Location in Octal
Control Line Pseudo-Instructions        ******* Optional        EQU     Decimal or Symbolic                     Equals
Control Line Pseudo-Instructions        ******* Optional        EQO     Octal                   Equals Octal
Control Line Pseudo-Instructions        ******* Optional        BSS     Decimal or Symbolic                     Block Started by Symbol
Control Line Pseudo-Instructions        *******         SBR     Symbol of Subroutine                    Subroutine Call
Control Line Pseudo-Instructions        *******         TCD     Decimal or Symbolic                     Transfer Punched Card
Control Line Pseudo-Instructions        *******         END     Decimal or Symbolic                     End of Program
Control Line Pseudo-Instructions        *******         REM                             Remarks
Additional Pseudo-Instructions  *******         EJT                             Eject Printer Paper
Additional Pseudo-Instructions  *******         SEQ                             Check Source Program Card Sequence Numbers
Additional Pseudo-Instructions  *******         NAM                             Print Name or Title on Each Page
Additional Pseudo-Instructions  *******         NLS                             No List
Additional Pseudo-Instructions  *******         LST                             List

        0100000         ADD     Y       X       2       Add
        0200000         SUB     Y       X       2       Substract
        1100000         DAD     Y       X       3       Double-Length Add
        1200000         DSU     Y       X       3       Double-Length Substract
        2504032         ADO                     2       Add One
        2504112         SBO                     2       Substract One
        1500000         MPY     Y       X       5-23    Multiply
        1600000         DVD     Y       X       26-29   Divide  
        2506011         SET     DECMODE         2       Set Decimal Mode        
        2506012         SET     BINMODE         2       Set Binary Mode 

Memory Transfers        0000000         LDA     Y       X       2       Load A  
Memory Transfers        1000000         DLD     Y       X       3       Double-Length Load      
Memory Transfers        0300000         STA     Y       X       2       Store A 
Memory Transfers        1300000         DST     Y       X       3       Double-Length Store     
Memory Transfers        2700000         STO     Y       X       2       Store Operand Address   
Memory Transfers        2300000         ORY     Y       X       2       Or A into Y     
Memory Transfers        2500111         OGA                     2       Or G into A     
Memory Transfers        2000000         EXT     Y       X       2       Extract 
Memory Transfers        2400000         MOV     Y               4+2N    Move (an optional feature)      
Arithmetic Register Transfers   2504001         LAQ                     2       Load A from Q   
Arithmetic Register Transfers   2504004         LQA                     2       Load Q from A   
Arithmetic Register Transfers   2504006         MAQ                     2       Move A to Q     A -> Q ; 0 -> A
Arithmetic Register Transfers   2504005         XAQ                     2       Exchange A and Q        Q -> temp ; A -> Q ; temp -> A
Arithmetic Register Transfers   2504202         LAC                     2       Load A from C-register (an optional feature)    C -> A
Arithmetic Register Transfers   2504210         LCA                     2       Load C-register from A (an optional feature)    A -> C
Register Modification   2504002         LDZ                     2       Load ZERO into A        0 -> A
Register Modification   2504022         LDO                     2       Load ONE into A 1 -> A
Register Modification   2504102         LMO                     2       Load MINUS ONE into A   -1 -> A
Register Modification   2504502         CPL                     2       Complement A    1's Complement A
Register Modification   2504522         NEG                     2       Negate A        2's Complement A
Register Modification   2504040         CHS                     2       Change Signe of A       
Register Modification   2504012         NOP                     2       No Operation    
Shifting        2510000         SRA     K       X       2-6     Shift Right A   
Shifting        2512000         SLA     K       X       2-6     Shift Left A    
Shifting        2511000         SRD     K       X       2-6     Shift Right Double (A and Q)    
Shifting        2512200         SLD     K       X       2-6     Shift Left Double (A and Q)     
Shifting        2510040         SCA     K       X       2-6     Shift Circular A        
Shifting        2511200         SCD     K       X       2-6     Shift Circular Double   
Shifting        2510400         SAN     K       X       2-6     Shift A and N Right
Shifting        2510100         SNA     K       X       2-6     Shift N and A Right
Shifting        2511400         ANQ     K       X       2-6     Shift A into N and Q
Shifting        2511100         NAQ     K       X       2-6     Shift N, A and Q Right
Shifting        2513000         NOR     K       X       3-7     Normalize A
Shifting        2513200         DNO     K       X       3-7     Double-Length Normalize
Internal Branching      2600000         BRU     Y       X       1       Branch Unconditionally
Internal Branching      0700000         SPB     Y       X       2       Store P and Branch
Test and Branch 2514003         BOV                     2       Branch on Overflow
        2516003         BNO                     2       Branch on No Overflow
        2516101         BPL                     2       Branch on Plus
        2514001         BMI                     2       Branch on Minus
        2504000         BOD                     2       Branch on Odd
        2516000         BEV                     2       Branch on Even
        2514002         BZE                     2       Branch on Zero
        2516002         BNZ                     2       Branch on Nonzero
        2514004         BPE                     2       Branch on Parity Error
        2516004         BPC                     2       Branch on Parity Correct
        2100000         CAB     Y       X       2-3     Compare and Branch (an optional feature)
        2200000         DCB     Y       X       2-5     Double Compare and Branch (an optional feature)
        2504010         WAI                     2       Who am I?
        1400000         INX     K       X       3       Incrimelt X
        0500000         BXH     K       X       2       Branch if X is Higher than or equal to
        0400000         BXL     K       X       2       Branch if X is less than
        0600000         LDX     Y       X       3       Load X
        1700000         STX     Y       X       3       Store X
        2506YY3         SXG     Y               2       Select X Group (an optional feature)
        2514PCC         BCS     XXX     P       4-6     Branch on Controller Selector
        2516P2C         BCS     XXX     P       4-6     Branch on Controller Selector
        2500P20         SEL     P       X       4-6     Select
Typeeriter Instruction  2500007         TON                     2       Typewriter On
Typeeriter Instruction  2500013         KON                     2       Keyboard On
Typeeriter Instruction  2500006         TYP                     2       Type
Typeeriter Instruction  2500005         OFF                     2       N-Register Logical Connections Off
Typeeriter Instruction  2516005         BNN                     2       Branch on N-Register Not Ready
Typeeriter Instruction  2514005         BNR                     2       Branch on N-Register Ready
Operator's Console Instruction  2500011         RCS                     2       Read Control Switches
API Instruction 2506015         SET     PST             2       Set Priority Start
API Instruction 2506016         SET     PBK             2       Set Priority Break